Electrono launches VLSI training program
Electrono Solutions Pvt.Ltd. is a design
consultancy and automation solutions provider for the Industry and Academia launched
the VLSI chip design program for BE/B.Tech and ME/M.Tech students. The training program aims
to teach students to understand the nuances of designing a chip in an optimized
way with maximum functionalities. By attending this training, participants would
get exposure to work on specialized / latest industrial softwares.
VLSI training program is specially designed for people who are interested to pursue a career in IC design. This training is a step taken by Electrono Solutions to bridge the gap between the industry and academia. The session would be handled by Industry experts specialised in the field of VLSI design.
The training module is as follows:
Digital Design Module |
Verilog Language Module
|
|
Digital Design Fundamentals Level 1
- Combinatorial Designs
- Sequential Designs
Digital Design Fundamentals Level 2
- Synchronous Sequential Logic
- Asynchronous Sequential Logic
- Baby sitting classes on Programmable Logic devices
- Introduction to ‘Analytical thinking for Digital designs’
- Principles of Digital design
- Finite State Machines
- Single Clock domain designs
- Multiple Clock domain designs
- Designing Synchronizer circuits
- Introduction to ASIC designs
- Basics on implementing DSP Algorithms
|
|
|
Level 1
- RTL Design overview
- Verilog language concepts
- Defining Modules and Ports
- ISE for HDL usage
- Introduction to Test benches
Level 2
- Operators, Dataflow
- Procedural Statements
- Controlled Operation Statements
- Tasks and Functions
- Modeling Finite State Machines
- Advance Language Concepts
- Advanced Verilog Test benches
- Modeling Synchronous design techniques
Level 3
- Modeling Verilog Code for Synthesis
- Modeling Verilog Code for Simulation.
- Simulation models vs. Synthesis models
|
|
Digital Design Module
|
Level 1
- Introduction to FPGA
- Understanding FPGA Components
- Basic FPGA Architecture - Spartan 6
- Configuring FPGA Devices (Configuration Process, Pins Assignment and UCF)
Level 2
- Developing Synchronous Designs for targeted FGPA
- HDL Coding Techniques for FPGA
- FPGA Selection Techniques for a Design
- Understanding FPGA Synthesis Techniques & Understanding Implementation Options
- Defining and Achieving Timing Closures
- Defining Path Specific Constraints
- Define design for Area or Speed
Level 3
- Xilinx and Lattice Tool Flow
- Reading Reports
- Implementing IP cores
- Pin Planning using Plan Ahead
- Static timing Analysis
- Global timing Constraints
|